With development of semiconductor technology, the feature size of semiconductor devices in integrated circuit (IC) devices has been reduced. Also, it has become increasingly difficult to increase the number of semiconductor devices in a two-dimensional (2D) package structure. Three-dimensional (3D) packaging becomes an effective tool to improve integration degree of IC devices or chips. The 3D packaging methods may include die stacking and package stacking based on gold wire bonding, and 3D stacking based on through-silicon vias (TSVs). The TSV-based 3D stacking technology may provide advantages including (1) high-density integration; (2) significantly-shortened-length of electrical interconnect, which solves signal delays and other problems occurring in a 2D system-on-chips (SOCs); and (3) integration of chips with different functions (e.g., RF, memory, logic, MEMS, etc.) to achieve versatility of the packaged devices.
Existing methods of forming a through-silicon via (TSV) include: forming a through-hole at a first surface of the silicon substrate by dry etching; forming an insulating layer on the sidewall and bottom surfaces of the through-hole; filling the through-hole with copper by an electroplating process; removing excess copper by a chemical mechanical polishing (CMP) process; polishing a second surface of the silicon substrate opposite to the first surface until the filled copper is exposed to form the TSV. The formed TSV can electrically connect a semiconductor device in the silicon substrate to another semiconductor device in another silicon substrate.
Currently, the insulating layer is typically made of silicon oxide and the silicon substrate is made of silicon. When forming the TSV by copper, a high temperature is usually used. Under this high temperature, due to different thermal expansion coefficients, mismatched thermal expansion may occur to the materials involved including copper, silicon, and silicon oxide. For example, copper has a higher thermal expansion coefficient than silicon. At high temperatures, the volume increase of the through-hole is not sufficient to accommodate thermal expansion of the TSV copper. Consequently, copper may be extruded from the TSV top surface, which affects yield and reliability of the thermal process and/or electrical properties of the resulting device.
As shown in FIG. 1, the TSV copper may be extruded from the through-hole 01 to form a copper protrusion 02. Due to existence of the copper protrusion 02, the metal layer 03 and the inter-layer dielectric layer 04 formed thereon have a non-flat surface, which generates device defects. When an interconnect structure is formed on surface of the TSV copper, the copper protrusions affect the electrical properties of this interconnect structure, and may cause a short circuit or open circuit. Further, even when the temperature is reduced to room temperature after formation of the TSV, copper shrinks and the copper extrusion still exists. This is because the copper lattice has been re-arranged during the thermal expansion, which cannot be recovered to its original form when cooling.
Thus, there is a need to overcome these and other problems of the prior art and to provide an IC device having a package structure and method for forming the IC device.